基于端口粒度故障定级管理的 NoC 容错架构设计

Design of NoC Fault-Tolerant Architecture Based on Port-Granularity Fault Grading Management

摘要

随着半导体工艺持续演进至深亚微米节点,片上网络关键组件在高密度集成环境下,面临日益严峻的物理缺陷与电噪声干扰,故障发生概率显著上升．现有容错机制在处理多类型并发故障时,常因故障模式识别精度不足,导致资源利用率偏低与通信性能下降．针对上述问题,本文提出一种基于端口粒度的故障定级管理容错架构,设计三级协同故障管控机制．首先,引入信用返还标识确认机制,实现链路层端口的亚周期级实时故障检测,能够精确定位并快速上报报文丢失与数据校验错误,显著提高故障检测准确率与响应速度；其次,设计轻量化备份缓冲区并融合优先级调度策略,支持故障报文的快速跨步重传,有效降低重传延迟与带宽开销；最后,基于故障状态机模型动态评估端口故障等级,实现通信资源自适应调度,进一步提升系统整体资源利用率．此外,该架构集成了协同容错路由算法,可快速识别瞬态故障并实现端口重启,同时对永久性故障端口实施智能隔离与动态路径绕行,从而减少冗余重传并降低容错操作带来的带宽损失．实验结果表明,在多类故障并发的合成流量场景下,本文所提架构的饱和吞吐率较 FT-E2E 容错方案最高可提升 41.6%,较 EsyTest 容错方案最高可提升 26.2%,实现了系统可靠性与通信性能的协同优化．

Abstract

As semiconductor technology continues to advance into deep sub-micron nodes,key components of network-on-chip(NoC)face increasingly severe physical defects and electrical noise in highly integrated environments,leading to a significant rise in the probability of failures. Existing fault-tolerant mechanisms often struggle with multiple concurrent fault types due to insufficient fault-pattern recognition,resulting in low resource utilization and degraded communication performance. To address these challenges,this paper proposes a port-granularity fault grading management architecture,which features a three-level cooperative fault-control mechanism. First,a credit-return identification and acknowledgment mechanism is introduced to achieve sub-cycle real-time fault detection at the link-layer port,enabling accurate localization and timely reporting of packet loss and data-corruption errors,thereby significantly improving fault-detection accuracy and response speed. Second,a lightweight backup buffer combined with a priority scheduling strategy supports fast hop-by-hop retransmission of faulty packets,effectively reducing retransmission latency and bandwidth overhead. Third,a fault-state machine model dynamically assesses port-fault levels and enables adaptive scheduling of communication resources,further enhancing overall system resource utilization. Additionally,the architecture integrates a cooperative fault-tolerant routing algorithm capable of rapid identification and recovery from transient faults,along with intelligent isolation and dynamic rerouting for permanent faults,which reduces redundant retransmissions and minimizes the bandwidth loss introduced by fault-tolerant operations. Experimental results show that,under synthetic traffic scenarios with multiple concurrent fault types,the proposed architecture achieves up to 41.6% higher saturation throughput compared to the FT-E2E fault-tolerant scheme and up to 26.2% higher than the EsyTest scheme,thereby achieving a synergistic optimization of system reliability and communication performance.

关键词

片上网络 / 容错架构 / 故障定级 / 可靠通信

Key words

network-on-chip(NoC) / fault-tolerant architecture / fault grading / reliable communication

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基金资助

天津市科技计划资助项目(22JCYBJC00140)