基于RFC型运放的低功耗高精度 Sigma Delta 调制器

A Low-Power High-Precision Sigma-Delta Modulator Based on an RFC-Type Operational Amplifier

摘要

模数转换器(ADC)是物联网(IoT)传感节点的核心组件．由于电池供电与微弱信号检测等应用条件，要求 ADC 兼具高精度与低功耗特性．为满足 IoT 传感节点对低频信号的高精度量化需求，设计一款高精度、低功耗的离散时间 sigma delta 调制器．调制器采用 3 阶单比特量化架构，在过采样率为 500 的条件下，理论可实现 169.3 dB 量化噪声信噪比．针对运放在高频时钟下的快速建立导致的静态功耗浪费问题，第 1 级积分器采用电流回收型折叠共源共栅(RFC)运放．该结构通过动态电流调度机制，在积分阶段从电源汲取较大电流以满足信号建立需求，而在非积分阶段消耗较少偏置电流，有效降低了持续工作下的平均功耗．相比传统折叠共源共栅(FC)结构，在相同带宽与摆率性能下，其静态偏置电流仅为后者的 38%．基于对运放建立过程中的信号完整性分析，提出了一种时序优化方案．该方案通过延长积分相时间，放宽了对运放的带宽与摆率要求，进一步实现调制器静态偏置电流的降低．该调制器基于 0.18 µm CMOS 工艺设计，在 1.8 V 电源电压下，平均功耗 408.3 µW．调制器版图面积为 520 µm×860 µm．后仿真结果表明，在 1.831 kHz 输入信号条件下，调制器输出比特流的信噪失真比可达 117.3 dB，有效位数为 19.19 bit，品质因数达 184.2 dB，适用于无人值守低功耗传感系统、便携式检测设备等场景．

Abstract

An analog-to-digital converter(ADC)is a core component in internet of things(IoT) sensing nodes. Battery-powered operation and weak signal detection require the ADC to provide high precision and low power consumption. To meet the demand for high-precision quantization of low-frequency signals，a discrete-time sigma-delta modulator was designed. The modulator employed a third-order single-bit architecture，theoretically achieving a 169.3 dB signal-to-quantization-noise ratio at an oversampling ratio of 500. To reduce static power waste caused by rapid operational amplifier settling under high-frequency clocking，a recycling folded cascode(RFC)operational amplifier was used in the first integrator. This structure incorporated a dynamic current-scheduling mechanism that draws higher current from the power supply during the integration phase to meet settling requirements，while maintaining a lower static bias during the nonintegration phase，thereby significantly reducing average power consumption in continuous operation. Compared with a conventional folded cascode(FC)amplifier of equivalent bandwidth and slew rate，the RFC amplifier consumes only 38% of the static bias current. A timing optimization scheme based on signal integrity analysis of the operational amplifier's settling behavior was proposed. By extending the integration phase duration，the scheme relaxed the operational amplifier's bandwidth and slew rate requirements，and further reduced the modulator's static bias current. Implemented in a 0.18 µm complementary metal-oxide semiconductor(CMOS) process，the modulator operated under a 1.8 V supply voltage with an average power consumption of 408.3 µW. The modulator layout occupied an area of 520 µm×860 µm. Post-simulation results showed that，for a 1.831 kHz input signal，the modulator achieves a signal-to-noise-and-distortion ratio of 117.3 dB，corresponding to an effective number of bits of 19.19，with a figure of merit of 184.2 dB，demonstrating its suitability for unattended low-power sensing systems and portable detection devices.

关键词

sigma delta 调制器 / 低采样热噪声 / 电流回收型折叠共源共栅运放 / 相位时间调节

Key words

sigma delta modulator / low sampling thermal noise / recycling folded cascode(RFC) operational amplifier / phase-time regulation

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基金资助

天津市自然科学基金资助项目(24JCQNJC01370)