A Wheatstone bridge-based frequency-locked loop （FLL） on-chip RC oscillator featuring high power supply rejection and low power consumption is proposed， which consists of a Wheatstone bridge， an error amplifier， a voltage-controlled oscillator （VCO）， a no-overlap clock generator and a low-dropout linear regulator （LDO）. The Wheatstone bridge conducts the frequency-to-voltage conversion on the VCO’s frequency through resistive-capacitive charging/discharging， improving frequency stability and reducing chip area， when compared with conventional designs. The LDO is adopted to supply the key modules in FLL， which essentially improve its power rejection. The VCO is accomplished through a cascaded inverter-based ring oscillator composed of high-threshold MOS transistors. By maintaining VCO’s supply voltage below the combined threshold voltages of high-threshold N/PMOS transistors， simultaneous conduction of these N/PMOSs is effectively prevented， cutting down the power consumption greatly. Theoretical analysis of oscillator operation， small-signal modeling of the FLL， and circuit-level implementation are presented in this paper. The oscillator is fabricated in CSMC 180 nm BCD technology and measured. As shown through measurement results， the oscillator’s frequency is locked to 1.98 MHz with 1% deviation from target， its frequency line sensitivity is less than 200 ×10-6 V across a 2.5~5.5 V supply range， the temperature-induced frequency drift is no more than 3% （250 ×10-6 ℃） from a temperature range of -20 ℃ to 100 ℃， and its total operating current is about 11.26 μA. Compared with state-of-the-art designs， the proposed FLL on-chip oscillator features low power consumption， high power rejection and a commendable figure of merit （FoM）.
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基金资助
国家自然科学基金资助项目(62371136)
National Natural ScienceFoundation of China(62371136)
京公网安备11010202008535号
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