应用于CMOS图像传感器的12 bit全局共用型列级SAR ADC

A 12 bit global shared column SAR ADC for CMOS image sensor

摘要

针对传统逐次逼近型模数转换器（SAR ADC）在CMOS图像传感器列级读出电路中的面积和功耗突出问题，提出一种面向大阵列的全局共用DAC型高速SAR ADC。该结构基于多列共用核心DAC的思想，将传统列级SAR ADC中面积需求最大的电容阵列DAC提取出来，采用不同权重的DAC信号，建立一个全局共用型DAC并采用多路选择加法器替代了传统的多列复用技术。该方法将每列SAR ADC简化后仅需要比较器、多路选择加法器以及部分数字逻辑，在保证SAR ADC的速度及精度优势的同时大幅度减小了其面积需求。基于55nm 1P4M CMOS工艺对所提出的方法进行了详细的电路设计和仿真验证，在模拟电压为3.3 V、数字电压为1.2 V、时钟频率为120 MHz、输入信号范围为1.6 V的情况下，设计实现的12-bit SAR ADC的静态参数DNL（differential nonlinearity）为−0.8/0.8 LSB，INL（integral nonlinearity）为−1.4/0.4 LSB，信噪失真比（SNR）达到68.24 dB，有效位数为11.02 bit，面积为10 μm×350 μm，功耗为264 μW。相比现有的SAR ADC，在保证SAR ADC高速、高精度的同时，也使ADC面积需求大幅度减小，为SAR ADC在高速CMOS图像传感器的列级读出电路中的应用提供了理论支撑。

Abstract

To address the issues of area and power consumption in traditional successive approximation register analog-to-digital converters (SAR ADCs) used in column-level readout circuits of CMOS image sensors, this paper proposes a high-speed SAR ADC with a globally shared DAC, tailored for large arrays. The proposed architecture is based on the concept of sharing a core DAC across multiple columns. It extracts the largest area-consuming component of traditional column-level SAR ADCs, the capacitor array DAC, and replaces it with a globally shared DAC that utilizes different weighted DAC signals, along with a multiplexer and adder, instead of traditional column-level multiplexing techniques. This method simplifies each column-level SAR ADC to only require a comparator, a multiplexer-adder, and partial digital logic, significantly reducing the area requirements while maintaining the speed and precision advantages of SAR ADCs. The proposed method was designed and simulated using a 55nm 1P4M CMOS process. With an analog voltage of 3.3V, a digital voltage of 1.2V, a clock frequency of 120MHz, and an input signal range of 1.6V, the 12-bit SAR ADC designed in this work achieves a static differential nonlinearity (DNL) of −0.8/0.8 LSB, an integral nonlinearity (INL) of −1.4/0.4 LSB, a signal-to-noise ratio (SNR) of 68.24 dB, and an effective number of bits (ENOB) of 11.02 bits. The total area is 10μm × 350μm, with a power consumption of 264 μW. Compared to existing SAR ADCs, this design reduces the area requirements significantly while maintaining high speed and precision, providing theoretical support for the application of SAR ADCs in the column-level readout circuits of high-speed CMOS image sensors.

关键词

CMOS图像传感器 / 列级ADC / SAR ADC / 全并行 / 全局共用

Key words

CMOS image sensor / column ADC / SAR ADC / fully parallel / global shared

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基金资助

国家自然科学基金(62171367)

陕西省创新能力支撑计划(2022TD-39)

西安理工大学校企协同基金(252062302)