基于特殊节点划分的低时延极化码SCL译码器架构

A low-latency architecture of SCL decoder for FPGA based on special node division

摘要

极化码基于信道极化理论提出，是唯一一种被理论证明可以达到香农限的信道编码方案。极化码主流的串行抵消列表（SCL）译码算法具有串行逐比特译码的特点，并且包含大量的路径度量和路径扩展，这导致译码时延较高。为了解决这一问题，提出了一种基于特殊节点划分的低时延SCL译码算法硬件架构，通过对不同类型的特殊节点分别使用剪枝或减分裂策略，以损失轻微译码性能为代价减少译码时延，提高吞吐量。为了提高译码器的灵活性，通过将不同码长码率的先验信息预先写入存储单元，从而实现编码参数可配置。可编程逻辑门阵列（FPGA）上的实验结果显示，在码长为128～1 024 bit以及码率为0.3～0.5的情况下，所提出的架构比标准SCL译码器降低了40.32%～56.87%的译码时延。

Abstract

Polar code proposed based on channel polarization is the only one that is proven to achieve the Shannon limit. The mainstream successive cancellation list (SCL) decoding algorithm shows the extremely high latency due to its massive path splitting and path metrics. To solve this problem, a low-latency SCL decoding hardware architecture based on special nodes is proposed in this paper. Pruning or split-reducing is considered for different nodes to reduce the decoding latency and improve the throughput with slight performance degradation. Moreover, to enhance the flexibility, the prior information of different code lengths and code rates is stored in the read-only memory (ROM) and is selected based on the input configuration. The implementation results of the proposed architecture on field programmable gate array (FPGA) show that the decoding cycles are reduced by 40.32%~56.87% compared with the standard SCL decoder with the code length varying from 128 to 1 024 bit and the code rate varying from 0.3 to 0.5.

关键词

极化码 / 串行抵消列表 / 低时延 / 可配置译码器 / 可编程逻辑门阵列

Key words

polar code / successive cancellation list / low latency / configurable decoder / FPGA

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基金资助

国家自然科学基金(62301166)

国家自然科学基金(62471151)

国家自然科学基金(62371101)