基于奇偶校验和循环冗余校验的增强Fast-SCL译码算法
韩国军 , 董鹏 , 曾子峰 , 翟雄飞 , 史治平
电子科技大学学报 ›› 2026, Vol. 55 ›› Issue (4) : 565 -570.
基于奇偶校验和循环冗余校验的增强Fast-SCL译码算法
Enhanced fast-SCL decoding based on parity check and cyclic redundancy check
极化码主流的快速串行消除列表(Fast-SCL)译码算法虽能实现低时延,但在中短码长下性能较差。针对该问题,提出了一种结合奇偶校验(parity check, PC)与循环冗余校验(CRC)的Fast-SCL算法。在Fast-SCL算法中引入PC位以实现早期的路径验证,提升路径选择的可靠性;同时,在校验位总数不变的前提下,考虑PC位与CRC位的多种组合方式。仿真结果表明,在短码长、帧错误率(FER)为10−2的条件下,与原始的CRC辅助Fast-SCL算法相比,该算法性能增益最高可达0.35 dB,计算复杂度最多可降低10%。
The fast successive cancellation list (Fast-SCL) decoding algorithm for polar codes can achieve low latency, but still performs poorly under medium and short code lengths. To deal with this issue, this paper proposes an improved Fast-SCL algorithm by combining parity check (PC) and cyclic redundancy check (CRC). Specifically, PC bits are introduced into the Fast-SCL algorithm to enable real-time path verification, which makes the path selection more reliable. Additionally, with the same total number of check bits, various combinations of PC bits and CRC bits are considered. The simulation results demonstrate that the proposed algorithm achieves a performance gain of 0.35 dB and a complexity reduction of 10% compared to the original CRC-assisted Fast-SCL algorithm under the short code lengths with the frame error rate (FER) being 10−2.
| [1] |
|
| [2] |
|
| [3] |
|
| [4] |
|
| [5] |
|
| [6] |
|
| [7] |
|
| [8] |
|
| [9] |
|
| [10] |
|
| [11] |
|
| [12] |
|
| [13] |
|
| [14] |
|
| [15] |
|
| [16] |
|
| [17] |
张宇 . Polar码译码算法研究及FPGA实现[D]. 成都: 电子科技大学,2023. |
| [18] |
|
| [19] |
曾子峰 . 极化码低时延SCL译码器研究与设计[D]. 广州: 广东工业大学,2025. |
| [20] |
|
| [21] |
王涛, 屈代明, 江涛 . 降低SCL译码错误的级联极化码[J].中兴通讯技术, 2019, 25(1): 5-11. |
| [22] |
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国家自然科学基金(62301166)
国家自然科学基金(62471151)
国家自然科学基金(U2001203)
国家自然科学基金(62371101)
广州市科技计划项目(2025A04J2904)
广东省重点领域研发计划“芯片、软件与计算(芯片类)”专项计划(2021B1101270001)
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